1. Field of the Invention
The present invention relates generally to integrated circuit testing, and more particularly to boundary scan testing of integrated circuits.
2. Description of the Background Art
The use of boundary scan testing of integrated circuits (“ICs”) is well known (an IC for purposes of this disclosure includes an ASIC and any other similar semiconductor device). Industry standards for boundary scan testing have been promulgated by IEEE as 1149.1 Standard Test Access Port and Boundary Scan Architecture, also known as JTAG in the United States. Information on the IEEE 1149.1 is available over the Web at, among other sources, http://www.ti.com and www.jtag.com.
Numerous commercial applications are available which automate the design of JTAG-compliant test port and scan logic architecture for a given IC design, and the subsequent testing of the fabricated IC using the JTAG-compliant scan logic. For example, BSD (Boundary-Scan Device) COMPILER, manufactured by SYNOPSIS CORPORATION of Mountain View, Calif., is a tool for automated synthesis and verification (among other things) of JTAG-compliant boundary scan logic in ICs. BSD COMPILER also automatically generates a BSDL (boundary scan description language) file describing the particular JTAG-compliant boundary scan design, which may be used for testing purposes. (BSDL is an industry standard description language for devices complying with the IEEE 1149.1.)
FIG. 1 schematically illustrates a conventional boundary scan architecture compliant with IEEE 1149.1. In FIG. 1, an IC 102 includes a single ended core logic 110, a plurality of input/output (I/O) nodes 100, and JTAG compliant boundary scan logic (dotted boxes 106 and 108). Boundary scan logic (dotted boxes 106 and 108) may be divided into boundary scan register (hereafter “scan register”) 106 and control logic block 108 for purposes of this disclosure. Scan register 106 includes a plurality of boundary scan cells (hereafter “scan cells”) 104 connected in series (and data flow direction) 104A–104F respectively. Each scan cell 104A–104F is coupled to an I/O node 100A–100F respectively. For purposes of this disclosure, an I/O node includes an I/O pin, an I/O pad, an I/O port, or any similar I/O interface for an IC 102. Please note that an I/O node may be bi-directional (i.e., accommodate input and output signals). JTAG-compliant control logic block 108 includes a bypass register 114, an instruction register 116, optional data register 118, TAP (Test Access Port) controller 120, and other logic omitted for purposes of ease of description. Control lines from control logic block 108 to each of the scan cells 104 are also omitted to facilitate description.
In operation, each scan cell 104 operates generally in two modes: scan test mode and normal mode. In scan test mode, scan cells 104 typically perform one of the following: capture data from input nodes 100A–100C, drive data to output nodes 100D–100F, scan in test data carried on TDI signal 110 into scan register 106 from input I/O node 10G, or scan out test data carried on TDO signal 112 to output I/O node 100H. In normal mode, input data signals 103A–103C are received from input I/O nodes 100A–100C and passed directly through scan cells 104A–104C without additional processing (e.g., capturing) by the scan cells 104A–104C; input data signals 103D–103F are likewise received from single ended core logic 110 and passed directly through scan cells 104D–104F without processing (e.g., capturing) by the scan cells 104D–104F. Scan cell 104 functions are controlled by control logic block 108. In particular, in JTAG-compatible control logic blocks, TAP controller 120 receives test mode select (“TMS”) signals 122 via I/O node 100J, which—in combination with instruction register 116, bypass register 114, and optional data register 118—control operation of scan register 106. TAP controller 120 typically receives TMS signals 122 from commercially available JTAG design and testing applications operating on a test computer system (shown as 204 in the FIG. 2). JTAG compliant boundary scan logic (dotted boxes 1.06 and 108) operates synchronously with test clock signal (“TCK”) 124 received via I/O node 1001.
FIG. 2 schematically illustrates a common use of JTAG boundary scan logic to test the interconnecting nets (open/short) of a printed circuit board (“PCB”), referred to also as a “board-level test.” In FIG. 2, PCB 202 includes multiple JTAG-compliant ICs 102-1 to 102-n connected in series for performing a board-level test. The scan registers 106 for each IC 102 are connected in series to form a single longer scan register consisting of the individually connected scan registers 106. In particular, TDO output nodes, e.g., 100H-1 to 100H-2, of each scan register 102 in the series, are connected to the TDI input nodes, e.g., 100G-2 to 100G-n, of the next scan register in the series. The TDO output node 100H-n of the last scan register 102-n in the series, and the TDI input node of the 100G-1 first scan register 106-1 in the series, are then connected to a TAP control device 204 via a test connector 206. It should be noted that not all of the ICs 102 on the PCB 202 need to be interconnected to perform board-level testing, as testing only a portion of a PCB may be desirable. TAP control device 204 is typically a computer system running a commercially available JTAG design and testing application. Connecting the IC-specific scan registers 106 into a single large scan register enables scan test data stored on TAP control device 204 to be scanned into and scanned out of the scan registers 106 by the TAP control device 204 for testing purposes.
The I/O nodes 100A to 100F of each IC 102 (reference numerals for each I/O node in FIG. 2 are not shown to avoid clutter) are interconnected according to the particular design requirements of the PCB 202, thereby defining the board-level nets to be tested. In FIG. 2, the output I/O nodes of each IC 102 in the series are connected to the corresponding input I/O nodes of the next IC 102 in the series, although an output I/O node may be connected to one or more input I/O nodes of any IC 102 on a PCB depending on the design requirements of the PCB. Accordingly, for example, output I/O node 100E-1 in IC 102-1 is connected to input I/O node 100B-2 in IC 102-2, thereby forming net 208. Boundary scan testing enables the integrity of net 208 to be tested by, for example, scanning in test data into scan cell 104E-1, driving a signal carrying the test data across net 208, capturing the signal in scan cell 104B-2, and then scanning out the captured data from scan cell 104B-2 back to the TAP control device 204 for analysis. In this manner, the integrity of net 208, and all of the nets generally included in PCB 202, may be determined by TAP control device 204 in a cost-efficient manner. Other types of testing (besides board-level testing) are available using boundary scan logic, such as functional testing of the IC and PCB (e.g., JTAG intest instruction), among other possibilities.